R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 225

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 16.29
Slave Address Register
IIC bus Transmit Data Register
b7 b6
NOTE :
b7 b6 b5 b4 b3 b2 b1
NOTE :
1.
1. Refer to 16.3.8.1 Accessing of Registers Associated w ith I
b5
Ref er to 16.3.8.1 Acce s s ing of Re gis te rs As s ociate d w ith I
Dec 08, 2006
b4
b3 b2
Registers SAR and ICDRT
b1
b0
b0
Store transmit data
When it is detected that the ICDRS register is empty, the stored transmit data item is
transferred to the ICDRS register and data transmission starts.
When the next transmit data item is w ritten to the ICDRT register during transmission of the
data in the ICDRS register, continuous transmit is enabled. When the MLS bit in the ICMR
register is set to 1 (data transferred LSB-first) and after the data is w ritten to the ICDRT
register, the MSB-LSB inverted data is read.
Bit Symbol
Symbol
Symbol
SVA0
SVA1
SVA2
SVA3
SVA4
SVA5
SVA6
ICDRT
SAR
(1)
Page 207 of 315
FS
(1)
Format select bit
Slave address 6 to 0
Address
Bit Name
00BDh
Address
00BEh
Function
0 : I
1 : Clock synchronous serial f ormat
Set an address dif f erent f rom that of the other
slave devices w hich are connected to the I
bus.
When the 7 high-order bits of the f irst f rame
transmitted af ter the starting condition match
bits SVA0 to SVA6 in slave mode of the I
bus f ormat, the MCU operates as a slave
device.
2
2
C bus Inte rface f or more inf ormation.
C bus Interface for more information.
2
C bus format
16. Clock Synchronous Serial Interface
Af ter Reset
Function
After Reset
00h
FFh
2
C
2
C
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW