R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 223

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 16.27
IIC bus Interrupt Enable Register
b7 b6 b5 b4
NOTES :
1.
2.
3.
An overrun error interrupt request is generated w hen the clock synchronous format is used.
Set the STIE bit to 1 (enable stop condition detection interrupt request) w hen the STOP bit in the ICSR register is set
to 0.
Refer to 16.3.8.1 Accessing of Registers Associated w ith I
Dec 08, 2006
b3 b2 b1
ICIER Register
b0
Bit Symbol
ACKBR
Symbol
ACKBT
NAKIE
ACKE
ICIER
STIE
TEIE
RIE
TIE
Page 205 of 315
Transmit acknow ledge
select bit
Receive acknow ledge bit
Acknow ledge bit judgment
select bit
Stop condition detection
interrupt enable bit
NACK receive interrupt
enable bit
Receive interrupt enable
bit
Transmit end interrupt
enable bit
Transmit interrupt enable
bit
(3)
Address
Bit Name
00BBh
0 : 0 is transmitted as acknow ledge bit in
1 : 1 is transmitted as acknow ledge bit in
0 : Acknow ledge bit received from
1 : Acknow ledge bit received from
0 : Value of receive acknow ledge bit is ignored
1 : When receive acknow ledge bit is set to 1,
0 : Disables stop condition detection interrupt
1 : Enables stop condition detection interrupt
0 : Disables NACK receive interrupt request and
1 : Enables NACK receive interrupt request and
0 : Disables receive data full and overrun
1 : Enables receive data full and overrun
0 : Disables transmit end interrupt request.
1 : Enables transmit end interrupt request.
0 : Disables transmit data empty interrupt request.
1 : Enables transmit data empty interrupt request.
receive device in transmit mode is set to 0.
receive device in transmit mode is set to 1.
and continuous transfer is performed.
continuous transfer is halted.
request.
request.
arbitration lost / overrun error interrupt request.
arbitration lost / overrun error interrupt request.
error interrupt request.
error interrupt request.
receive mode.
receive mode.
2
C bus Interface for more information.
(2)
16. Clock Synchronous Serial Interface
After Reset
Function
00h
(1)
(1)
RW
RW
RW
RW
RW
RW
RW
RW
RO