R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 246

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 16.47
NOTES:
1. Do not generate the interrupt while processing steps (1) to (3).
2. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to process of step (7).
Dec 08, 2006
Processing step (8) is dummy read of the ICDRR register.
ICSR register
ICCR1 register
ICSR register
ICIER register ACKBT bit ← 0
ICIER register ACKBT Bit ← 1
ICCR1 register RCVD Bit ← 1
ICSR register
ICCR2 register
ICCR1 register RCVD bit ← 0
ICCR1 register
Example of Register Setting in Master Receive Mode (I
Read STOP bit in ICSR register
Read RDRF bit in ICSR register
Read RDRF bit in ICSR register
Dummy read in ICDRR register
No
No
No
Read ICDRR register
Read ICDRR register
Read ICDRR register
Master receive mode
RDRF = 1 ?
Yes
RDRF = 1 ?
Yes
Yes
Last receive
STOP = 1 ?
Page 228 of 315
TEND bit ← 0
TDRE bit ← 0
STOP bit ← 0
BBSY bit ← 0
MST bit ← 0
- 1 ?
TRS bit ← 0
SCP bit ← 0
End
No
Yes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(1) Set the TEND bit to 0 and set to master receive mode.
(2) Set the ACKBT bit to the transmit device.
(3) Dummy read the ICDRR register
(4) Wait for 1 byte to be received.
(5) Judge (last receive - 1).
(6) Read the receive data.
(7) Set the ACKBT bit of the last byte and set to disable the
(8) Read the receive data of (last byte - 1).
(9) Wait until the last byte is received.
(10) Set the STOP bit to 0.
(11) Generate the stop condition.
(12) Wait until the stop condition is generated.
(13) Read the receive data of the last byte.
(14) Set the RCVD bit to 0.
(15) Set to slave receive mode.
continuous receive operation (RCVD = 1).
Set the TDRE bit to 0.
16. Clock Synchronous Serial Interface
2
(1,2)
C bus Interface Mode)
(1)
(1)
(2)