R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 121

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
13. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows
selection of count source protection mode enable or disable. Table 13.1 lists information on the Count Source
Protection Mode.
Refer to 6.5 Watchdog Timer Reset for details on the watchdog timer reset.
Figure 13.1 shows the Block Diagram of Watchdog Timer and Figures 13.2 to 13.3 show Registers OFS, WDC,
WDTR, WDTS, and CSPR.
Figure 13.1
Table 13.1
Count source
Count operation
Reset condition of watchdog
timer
Count start condition
Count stop condition
Operation at time of underflow
CPU clock
NOTE:
Dec 08, 2006
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
Write to WDTR register
reset signal
Count Source Protection Mode
Block Diagram of Watchdog Timer
Item
Internal
Page 103 of 315
Prescaler
1/128
1/16
CPU clock
Decrement
• Reset
• Write 00h to the WDTR register before writing FFh
• underflow
Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Stop mode, wait mode
Watchdog timer interrupt or
watchdog timer reset
Count Source Protection Mode
WDC7 = 1
WDC7 = 0
fRING-S
Disabled
CSPRO = 0
CSPRO = 1
Watchdog timer
Low-speed on-chip oscillator
clock
None
Watchdog timer reset
Count Source Protection Mode
Set to
7FFFh
(1)
CSPRO: Bit in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
Enabled
13. Watchdog Timer
PM12 = 0
Watchdog timer
interrupt request
PM12 = 1
Watchdog
timer reset