R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 335

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
1.00
REVISION HISTORY
Sep 09, 2005
Date
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Table 5.18 Unassigned Pin Handling, Figure 5.11 Unassigned Pin
Handling;
Table 9.2 Bus Cycles for Access Space of the R8C/1B Group added,
Table 9.3 Access Unit and Bus Operation;
10.2.1 Low-speed On-Chip Oscillator Clock;
10.2.2 High-Speed On-Chip Oscillator Clock;
10.5.1 How to Use Oscillation Stop Detection Function;
Figure 10.9 Procedure of Switching Clock Source From Low-Speed On-
Chip Oscillator to Main Clock revised
10.6.2 Oscillation Stop Detection Function;
10.6.4 High-Speed On-Ship Oscillator Clock added.
Figure 12.10 Judgement Circuit of Interrupts Priority Level;
Figure 14.1 Block Diagram of Timer X;
14.1.6 Precautions on Timer X;
Figure 14.11 Block Diagram of Timer Z;
14.2.5 Precautions on Timer Z;
Figure 15.3 U0TB to U1TB, U0RB to U1RB and U0BRG to U1BRG
Registers;
Table 15.5 Registers to Be Used and Settings in UART Mode;
Table 16.1 Mode Selection;
16.2.8.2 Selecting SSI Signal Pin added
R8C/1A Group, R8C/1B Group Hardware Manual
“Port P4_2, P4_6, P4_7” → “Port P4_6, P4_7”
“VREF” → “Port P4_2/VREF” revised
“SFR” → “SFR, Data flash”,
“ROM/RAM” → “Program ROM, ROM, RAM” revised
“The application products ... to accommodate the frequency range.” →
“The application products ... for the frequency change.” revised
“The high-speed on-chip oscillator frequency ... for details.” added
“This function cannot ... is 2 MHz or below.” →
“This function cannot be ... is below 2 MHz.” revised
“Since the oscillation ...frequency is 2MHz or below, ...” →
“Since the oscillation ...frequency is below 2MHz, ...” revised
NOTE2 deleted
“Peripheral data bus” → “Data Bus” revised
“When writing “1” (count starts) to ... writing “1” to the TXS bit.” →
‘ “0” (count stops) can be read ... after the TXS bit is set to “1”.’ revised
“Peripheral Data Bus” → “Data Bus” revised
“When writing “1” (count starts) to ... writing “1” to the TZS bit.” →
‘ “0” (count stops) can be read ... after the TZS bit is set to “1”.’ revised
“UARTi Transmit Buffer Register (i=0 to 1)” and “UARTi Receive Buffer
Register (i=0 to 1)” revised
UiBRG: “ − ” → “0 to 7” revised
“RE and TE Bits in SSER Register” added
C - 2
Description
Summary