R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 228

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
16.3.2
Table 16.7
STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register
AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register
Transmit data empty
Transmit ends
Receive data full
Stop condition detection
NACK detection
Arbitration lost/overrun error
The I
synchronous serial format is used.
Table 16.7 lists the Interrupt Requests of I
Since these interrupt requests are allocated at the I
by each bit is necessary.
When the generation conditions listed in Table 16.7 are met, an I
Set the interrupt generation conditions to 0 by the I
TEND are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is
automatically set to 0 by reading the ICDRR register. When writing transmit data to the ICDRT register, the
TDRE bit is set to 0. When data is transferred from registers ICDRT to ICDRS, the TDRE bit is set to 1 and by
further setting the TDRE bit to 0, 1 additional byte may be transmitted.
Set the STIE bit to 1 (enable stop condition detection interrupt request) when the STOP bit is set to 0.
Dec 08, 2006
2
Interrupt Requests
C bus interface has six interrupt requests when the I
Interrupt Request
Interrupt Requests of I
Page 210 of 315
TXI
TEI
RXI
STPI
NAKI
2
C bus Interface
2
C bus Interface.
TIE = 1 and TDRE = 1
TEIE = 1 and TEND = 1
RIE = 1 and RDRF = 1
STIE = 1 and STOP = 1
NAKIE = 1 and AL = 1 (or
NAKIE = 1 and NACKF = 1)
Generation Condition
2
C bus interface interrupt vector table, determining the factor
2
C bus interface interrupt routine. However, bits TDRE and
2
C bus format is used and four when the clock
2
C bus interface interrupt request is generated.
16. Clock Synchronous Serial Interface
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
I
2
C bus
Format
Synchronous
Enabled
Enabled
Enabled
Disabled
Disabled
Enabled
Clock
Serial