R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 173

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/1A Group, R8C/1B Group
Rev.1.30
REJ09B0252-0130
Figure 15.4
UARTi Transmit / Receive Mode Register (i = 0 or 1)
b7 b6 b5 b4
NOTES :
0
1.
2.
3.
Set the PD1_6 bit in the PD1 register to 0 (input).
Do not set bits SMD2 to SMD0 in the U1MR register to any values other than 000b, 100b, 101b, and 110b.
Set the CKDIR bit in UART1 to 0 (internal clock).
Dec 08, 2006
b3 b2 b1
Registers U0MR to U1MR
b0
Bit Symbol
Symbol
CKDIR
U0MR
U1MR
SMD0
SMD1
SMD2
PRYE
STPS
PRY
(b7)
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—
Serial interface mode select
bits
Internal / external clock select
bit
Stop bit length select bit
Odd / even parity select bit
Parity enable bit
Reserved bit
(3)
(2)
Address
Bit Name
00A0h
00A8h
b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Other than above : Do not set.
0 : Internal clock
1 : External clock
0 : 1 stop bit
1 : 2 stop bits
Enabled w hen PRYE = 1.
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
Set to 0.
(1)
After Reset
Function
00h
00h
15. Serial Interface
RW
RW
RW
RW
RW
RW
RW
RW
RW