EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 105

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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AIIGX51005-4.0
Clock Networks in Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
December 2010
AIIGX51005-4.0
This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)
which have advanced features in Arria
networks (GCLKs), regional clock networks (RCLKs), and periphery clock networks
(PCLKs). This chapter also includes details reconfiguring the PLL counter clock
frequency and phase shift in real time, allowing you to sweep PLL output frequencies
and dynamically adjust the output clock phase shift.
This chapter contains the following sections:
■
■
The GCLKs, RCLKs, and PCLKs available in Arria II devices are organized into
hierarchical clock structures that provide up to 192 unique clock domains
(16 GCLK + 88 RCLK + 88 PCLK) and allow up to 60 unique GCLK, RCLK, and PCLK
clock sources (16 GCLK + 22 RCLK + 22 PCLK) per device quadrant.
“Clock Networks in Arria II Devices” on page 5–1
“PLLs in Arria II Devices” on page 5–19
5. Clock Networks and PLLs in Arria II
®
II devices that provide dedicated global clock
Devices
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