EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 566

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–8
Combining Receiver Only Channels
Arria II Device Handbook Volume 2: Transceivers
1
1
1
In cases where you have two instances with the same serial data rate but with
different CMU PLL data rates, the Quartus II software creates a separate CMU PLL
for the two instances. For example, consider the configuration shown in
Table 3–3. Sample Configuration Where Instances Cannot Be Combined in a Single Transceiver
Block for Arria II Devices
Even though the effective data rate of inst1 and inst0 are 1.5 Gbps
(3 Gbps/2 = 1.5 Gbps), when you compile the design, the Quartus II software requires
two CMU PLLs to provide clocks for the transmitter side of the two instances because
their base data rates are different. In this example, you have the third instance (inst2)
that requires a third CMU PLL. Therefore, the Quartus II software cannot combine the
above three instances within the same transceiver block.
You can selectively use the receiver in the transceiver channel by selecting the
Receiver Only configuration in the What is the Operating Mode? option on the
General screen of the ALTGX MegaWizard Plug-In Manager.
You can combine Receiver Only channel instances of different configurations and
data rates into the same transceiver block. Because each receiver channel contains its
own dedicated CDR, each Receiver Only instance (assuming one receiver channel per
instance) can have different data rates.
For the Quartus II software to combine the Receiver Only instances within the same
transceiver block, you must connect gxb_powerdown (if used) of all the channel
instances from the same logic or input pin. For more information, refer to
Requirements to Combine Channels” on page
It is possible to have up to four receiver channels that can run at different data rates by
using separate input reference clocks if there are enough clock routing resources
available.
If you instantiate the Receiver Only configuration, the ALTGX MegaWizard Plug-In
Manager does not allow you to enable the rate matching FIFO (clock rate
compensation FIFO) in the receiver channel PCS because tx_clkout is not available in
a Receiver Only instance to clock the read side of the rate matching FIFO. If you have
to perform clock rate compensation, implement the rate matching FIFO in the FPGA
fabric.
If you create a Receiver Only instance and do not use the transmitter channel that is
present in the same physical transceiver channel, the Quartus II software
automatically powers down the unused transmitter channel.
inst0
inst1
inst2
Instance Name
User-Created
Number of
Channels
1
1
1
Chapter 3: Configuring Multiple Protocols and Data Rates in Arria II Devices
ALTGX MegaWizard Plug-In Manager Settings
Receiver and Transmitter
Receiver and Transmitter
Receiver and Transmitter
Configuration
3–2.
Effective Data
Rate (Gbps)
December 2010 Altera Corporation
Combining Receiver Only Channels
1.5
1.5
1
Table
Rate (Gbps)
Base Data
“General
1.5
3.0
1
3–3.