EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 186

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–28
Termination Schemes for I/O Standards
Figure 6–11. SSTL I/O Standard Termination for Arria II Devices
Note to
(1) Applicable to Arria II GZ devices only.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
OCT
in Bi-
Directional
Pins (1)
Termination
External
On-Board
Termination
OCT
Receive (1)
OCT
Transmit
Figure
Single-Ended I/O Standards Termination
Series OCT
Series OCT
50
6–11:
Transmitter
Transmitter
Transmitter
Transmitter
50
V
CCIO
The following section describes the different termination schemes for I/O standards
used in Arria II devices.
Voltage-referenced I/O standards require both an input reference voltage (V
termination voltage (V
termination voltage of the transmitting device.
Figure 6–11
100
100
SSTL Class I
25
25
50
50 8
50
V REF
V REF
50
50
50
V REF
V REF
V TT
50
shows the details of SSTL I/O termination on Arria II devices.
V TT
V
V CCIO
CCIO
100
100
100
100
Receiver
Receiver
Receiver
TT
Parallel OCT
Series
OCT 50
). The reference voltage of the receiving device tracks the
Receiver
Series OCT
25
Series OCT
Transmitter
Transmitter
Transmitter
Transmitter
25
V
CCIO
100
100
25
25
50
V TT
SSTL Class II
50
Chapter 6: I/O Features in Arria II Devices
V TT
50
V TT
Termination Schemes for I/O Standards
50
50
50
December 2010 Altera Corporation
50
V REF
50
V REF
V REF
50
V TT
V TT
V
V
CCIO
CCIO
100
100
100
100
Receiver
Receiver
Receiver
Receiver
Series
OCT 25
Parallel OCT
R EF
) and a