EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 46

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–18
Document Revision History
Table 2–1. Document Revision History
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
June 2009
February 2009
Date
f
Version
■
For more information about implementing static and dynamic power consumption
within the LAB, refer to the
Handbook.
Table 2–1
2.0
1.1
1.0
Clocks represent a significant portion of dynamic power consumption due to their
high switching activity and long paths. The LAB clock that distributes a clock
signal to registers within an LAB is a significant contributor to overall clock power
consumption. Each LAB’s clock and clock enable signal are linked. For example, a
combinational ALUT or register in a particular LAB using the labclk1 signal also
uses the labclkena1 signal. To disable an LAB-wide clock power consumption
without disabling the entire clock tree, use the LAB-wide clock enable to gate the
LAB-wide clock. The Quartus II software automatically promotes register-level
clock enable signals to the LAB-level. All registers within the LAB that share a
common clock and clock enable are controlled by a shared, gated clock. To take
advantage of these clock enables, use a clock-enable construct in your HDL code
for the registered logic.
Updated for the Quartus II software version 10.1 release:
■
■
■
■
Updated Figure 2–6.
Initial Release.
Added Arria II GZ device information.
Updated
Logic
Added
Added
lists the revision history for this document.
Modules”,
Figure 2–7
“LAB Power Management Techniques”
“Logic Array
“ALM Operating
and
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Power Optimization
Blocks”,
Figure
2–8.
“LAB
Modes”,
Interconnects”,
Changes
“Normal Mode”
chapter in volume 2 of the Quartus II
section.
“LAB Control
sections.
December 2010 Altera Corporation
Signals”,
Document Revision History
“Adaptive