EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 485

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Transceiver Port List
Table 1–30. ALTGX Megafunction Receiver PMA Ports for Arria II Devices (Part 2 of 2)
Table 1–31. ALTGX Megafunction TX Phase Compensation FIFO Ports for Arria II Devices
December 2010 Altera Corporation
rx_locktorefclk
rx_seriallpbken
rx_seriallpbkin
tx_revseriallpbkin
rx_freqlocked
rx_pll_locked
rx_revseriallpbkout
tx_seriallpbkout
rx_signaldetect
tx_coreclk
tx_datain
tx_clkout
tx_phase_comp_fifo_
error
coreclkout
Port Name
Port Name
Table 1–31
ALTGX megafunction.
Input/Output
Input/Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
lists the TX phase compensation FIFO port names and descriptions for the
Optional write clock port for the TX phase compensation FIFO. If enabled, you
must drive this port with a clock that is frequency locked to
tx_clkout/coreclkout (with 0 PPM frequency difference).
Parallel data input from the FPGA fabric to the transmitter. The bus width
depends on the channel width multiplied by the number of channels per
instance.
FPGA fabric-transceiver interface clock. Each channel has a tx_clkout signal
in non-bonded channel configurations.
TX phase compensation FIFO full or empty indicator. A high level indicates that
the TX phase compensation FIFO is either full or empty.
Clock from the CMU0 block of the associated transceiver block or of the master
transceiver block for ×4 bonded or ×8 bonded channel configurations,
respectively. This is the default read and write clocks for those configurations.
Asynchronous receiver CDR LTR mode control signal.
The rx_locktorefclk and rx_locktodata signals control whether the
receiver CDR is in LTR or LTD mode, as follows:
rx_locktodata/rx_locktorefclk
0/0—receiver CDR is in automatic mode
0/1—receiver CDR is in LTR mode
1/x—receiver CDR is in LTD mode
Active-high serial loopback control port.
Input on a Receiver-only configuration when you enable serial loopback. You
must connect this port to the tx_seriallpbkout port.
Input on a Transmitter-only configuration when you enable reverse serial
loopback. You must connect this port to the rx_revseriallpbkout port.
Asynchronous receiver CDR lock mode indicator. A high level indicates that the
receiver CDR is in LTD mode. A low level indicates that the receiver CDR is in
LTR mode.
Asynchronous active high receiver CDR LTR indicator. The receiver CDR is
locked to the input reference clock.
Output on a Receiver-only configuration when you enable reverse serial
loopback. You must connect this port to the tx_revseriallpbkin port.
Output on a Transmitter-only configuration when you enable serial loopback.
You must connect this port to the tx_seriallpbkout port.
Asynchronous signal threshold detect indicator for PCIe mode only. A high
level indicates that the signal present at the receiver input buffer is above the
programmed signal detection threshold value.
If the electrical idle inference block is disabled in PCIe mode, the
rx_signaldetect signal is inverted and driven on the pipeelecidle port.
Description
Description
Arria II Device Handbook Volume 2: Transceivers
1–99