EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 128

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–24
Figure 5–19. External Clock Outputs for Left and Right PLLs in Arria II GZ Devices
Notes to
(1) You can feed these clock output pins using any one of the C[6..0], or m counters.
(2) The CLKOUT0p and CLKOUT0n pins are dual-purpose I/O pins that you can use as two single-ended outputs or one single-ended output and
(3) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
one external feedback input pin.
Figure
5–19:
f
1
PLL_<L2, L3, R2, R3>_CLKOUT0n/FB_CLKOUT0p (1), (2)
Each pin of a single-ended output pair can either be in-phase or 180° out-of-phase.
The Quartus II software places the NOT gate in your design into the IOE to
implement a 180° phase with respect to the other pin in the pair. The clock output pin
pairs support the same I/O standards as standard output pins, as well as LVDS_E_3R,
LVPECL, differential high-speed transceiver logic (HSTL), and differential SSTL.
To determine which I/O standards are supported by the PLL clock input and output
pins, refer to the
Arria II PLLs can also drive out to any regular I/O pin through the GCLK or RCLK
network. You can also use the external clock output pins as user I/O pins if you do
not require external PLL clocking. However, external clock output pins can support a
differential I/O standard that is only driven by a PLL.
Regular I/O pins cannot drive the PLL clock input pins.
Left/Right
PLLs
I/O Features in Arria II Devices
clkena0 (3)
m(fbout)
clkena1 (3)
PLL_<L2, L3, R2, R3>_FB_CLKOUT0p/CLKOUT0n (1), (2)
C0
C1
C2
C3
C4
C5
C6
Chapter 5: Clock Networks and PLLs in Arria II Devices
chapter.
Internal Logic
December 2010 Altera Corporation
PLLs in Arria II Devices