EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 98

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Arria II Device Handbook Volume 1: Device Interfaces and Integration
Shift Modes
1
1
The control signal for the accumulator and subtractor is static and therefore you can
configure it at compilation.
The multiply accumulate mode supports the rounding and saturation logic unit
because it is configured as an 18-bit multiplier accumulator. You can use the pipeline
registers and output registers within the DSP block to increase the performance of the
DSP block.
Arria II devices support the following shift modes for 32-bit input only:
■
■
■
■
■
You can switch the shift mode between these modes with the dynamic rotate and shift
control signals.
You can easily use the shift mode in an Arria II device with a soft embedded processor
such as the Nios
Shift mode makes use of the available multipliers to logically or arithmetically shift
left, right, or rotate the desired 32-bit data. The DSP block is configured like the
independent 36-bit multiplier mode to perform the shift mode operations.
Arithmetic shift right requires a signed input vector. During arithmetic shift right, the
sign is extended to fill the MSB of the 32-bit vector. The logical shift right uses an
unsigned input vector. During logical shift right, zeros are padded in the most
significant bits shifting the 32-bit vector to the right. The barrel shifter uses an
unsigned input vector and implements a rotation function on a 32-bit word length.
Two control signals, rotate and shift_right, together with the signa and signb
signals, determine the shifting operation.
Arithmetic shift left, ASL[N]
Arithmetic shift right, ASR[32-N]
Logical shift left, LSL[N]
Logical shift right, LSR[32-N]
32-bit rotator or Barrel shifter, ROT[N]
®
II processor to perform the dynamic shift and rotate operation.
Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
December 2010 Altera Corporation