EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 140

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–36
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Programmable Bandwidth
Spread-Spectrum Tracking
Clock Switchover
PLL bandwidth is the measure of the ability of the PLL to track the input clock and its
associated jitter. Arria II PLLs provide advanced control of the PLL bandwidth with
the PLL loop’s programmable characteristics, including loop filter and charge pump.
The closed-loop gain 3-dB frequency in the PLL determines the PLL bandwidth. The
bandwidth is approximately the unity gain point for open loop PLL response.
Arria II devices can accept a spread-spectrum input with typical modulation
frequencies. However, the device cannot automatically detect that the input is a
spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the
input of the PLL. Arria II PLLs can track a spread-spectrum input clock as long as the
input jitter is in the PLL input jitter tolerance specification. Arria II devices cannot
internally generate spread-spectrum clocks.
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application
such as in a system that turns on the redundant clock if the previous clock stops
running. Your design can perform clock switchover automatically, when the clock is
no longer toggling or based on a user control signal (clkswitch).
The following clock switchover modes are supported in Arria II PLLs:
■
■
■
Automatic switchover—The clock sense circuit monitors the current reference
clock and if it stops toggling, automatically switches to the other clock (inclk0 or
inclk1).
Manual clock switchover—Clock switchover is controlled with the clkswitch
signal in this mode. When the clkswitch signal goes from logic low to logic high,
and stays high for at least three clock cycles, the reference clock to the PLL is
switched from inclk0 to inclk1, or vice-versa.
Automatic switchover with manual override—This mode combines modes 1 and
2. When clkswitch = 1, it overrides automatic clock switchover function. As long
as the clkswitch signal is high, further switchover action is blocked.
Chapter 5: Clock Networks and PLLs in Arria II Devices
December 2010 Altera Corporation
PLLs in Arria II Devices