EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 541

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
December 2010 Altera Corporation
Because the recovered clock rx_clkout signals from all 16 channels have a 0 PPM
frequency difference, you can use a single rx_clkout to clock the receiver phase
compensation FIFO in all 16 channels, resulting in only one global or regional clock
resource being used instead of 16. To implement this clocking scheme, you must select
the receiver phase compensation FIFO read clocks instead of the Quartus II software
automatic selection, as described in the
FIFO Read Clock”
User-Selected Receiver Phase Compensation FIFO Read Clock
The ALTGX MegaWizard Plug-In Manager provides an optional rx_coreclk port for
each instantiated receiver channel. If you enable this port, the Quartus II software
does not automatically select the receiver phase compensation FIFO read clock source.
Instead, the signal that you drive on the rx_coreclk port of the channel clocks the
read side of its receiver phase compensation FIFO.
You can use the flexibility of selecting the receiver phase compensation FIFO read
clock to reduce clock resource utilization (global, regional, or both). You can connect
the rx_coreclk ports of all the receiver channels in your design and drive them using
a common clock driver that has a 0 PPM frequency difference with respect to the FIFO
write clocks of these channels. Use this common clock driver to latch the receiver data
and status signals in the FPGA fabric for these channels. This FPGA fabric transceiver
interface clocking scheme uses only one global or regional clock resource for all
channels.
section.
“User-Selected Receiver Phase Compensation
Arria II Device Handbook Volume 2: Transceivers
2–51