EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 130

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–26
Table 5–14. Clock Feedback Mode Availability for Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Source-synchronous mode
No-compensation mode
Normal mode
Zero-delay buffer (ZDB) mode
External Feedback
LVDS compensation
Notes to
(1) ZDB mode uses 8 ns delay for compensation in Arria II GX devices.
(2) The high-bandwidth PLL setting is not supported in the external feedback mode.
(3) External feedback mode is supported for single-ended inputs and outputs only on the left and right PLLs.
(4) LVDS compensation mode is only supported on PLL_2, PLL_3, PLL_5, and PLL_6.
Clock Feedback Mode
Table
Clock Feedback Modes
5–14:
1
(2)
Arria II PLLs support up to six different clock feedback modes. Each mode allows
clock multiplication and division, phase shifting, and programmable duty cycle.
Table 5–14
Input and output delays are fully compensated by a PLL only when you use the
dedicated clock input pins associated with a given PLL as clock sources. For example,
when you use PLL_1 (Arria II GX devices) or PLL_T1 (Arria II GZ devices) in normal
mode, the clock delays from the input pin to the PLL clock output-to-destination
register are fully compensated, provided the clock input pin is one of the following
four pins: CLK12, CLK13, CLK14, or CLK15. When an RCLK or GCLK network drives the
PLL, the input and output delays may not be fully compensated in the Quartus II
software. Another example is when PLL_1 (Arria II GX devices) or PLL_T2 (Arria II GZ
devices) is configured in zero delay buffer mode and the PLL input is driven by a
dedicated clock input pin, a fully compensated clock path results in zero delay
between the clock input and one of the output clocks from the PLL. If the PLL input is
instead fed by a non-dedicated input (using the GCLK network), the output clock
may not be perfectly aligned with the input clock.
(1)
lists the clock feedback modes supported by the Arria II PLLs.
Availability in Arria II GX Devices
Yes
Yes
Yes
Yes
Yes
No
(4)
Chapter 5: Clock Networks and PLLs in Arria II Devices
Top/Bottom PLLs
Availability in Arria II GZ Devices
Yes
Yes
Yes
Yes
Yes
No
December 2010 Altera Corporation
Left/Right PLLs
PLLs in Arria II Devices
Yes
Yes
Yes
Yes
Yes
Yes
(3)