EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 155

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–40. Dynamic Phase Shifting Waveform for Arria II Devices
December 2010 Altera Corporation
SCANCLK
PHASESTEP
PHASEUPDOWN
PHASECOUNTERSELECT
PHASEDONE
f
1
All signals are synchronous to SCANCLK and must meet the t
with respect to the SCANCLK edges. They are latched on SCANCLK edges and must meet
the t
You can repeat dynamic phase-shifting indefinitely. For example, in a design where
the VCO frequency is set to 1,000 MHz and the output clock frequency is set to
100 MHz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift)
results in shifting the output clock by 180°, in other words, a phase shift of 5 ns.
The PHASESTEP signal is latched on the negative edge of SCANCLK. In
shown by the second SCANCLK falling edge. PHASESTEP must stay high for at least two
SCANCLK cycles. On the second SCANCLK rising edge after PHASESTEP is latched (the
fourth SCANCLK rising edge in
PHASECOUNTERSELECT are latched and the PLL starts dynamic phase-shifting for the
specified counters and in the indicated direction. On the fourth SCANCLK rising edge,
PHASEDONE goes high to low and remains low until the PLL finishes dynamic
phase-shifting. You can perform another dynamic phase-shift after the PHASEDONE
signal goes from low to high.
Depending on the VCO and SCANCLK frequencies, phasedone low time (t
may be greater than or less than one SCANCLK cycle.
For more information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager
interface, refer to the
Megafunction User
su
and t
a
h
requirements with respect to the SCANCLK edges.
b
t
CONFIGPHASE
Guide.
PHASEDONE goes low synchronous with SCANCLK
Phase Locked-Loops Reconfiguration (ALTPLL_RECONFIG)
Figure
Arria II Device Handbook Volume 1: Device Interfaces and Integration
5–40), the values of PHASEUPDOWN and
c
d
su
and t
h
Figure
requirements
CONFIGPHASE
5–40, this is
5–51
)