EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 168

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–10
I/O Structure
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Table 6–6. Pin Migration Across Densities in Arria II GZ Devices
The I/O element (IOE) in the Arria II devices contains a bidirectional I/O buffer and
I/O registers to support a completely embedded bidirectional single data rate (SDR)
or double data rate (DDR) transfer. The IOEs are located in I/O blocks around the
periphery of the Arria II device. There are up to four IOEs per row I/O block and four
IOEs per column I/O block. The row IOEs drive row, column, or direct link
interconnects. The column IOEs drive column interconnects.
The Arria II bidirectional IOE supports the following features:
■
■
■
■
■
■
■
■
■
■
■
■
1152-pin Flip Chip
FBGA
1517-pin Flip Chip
FBGA
Note to
(1) Each transceiver channel consists of two Tx pins, two Rx pins and a transceiver clock pin.
Programmable input delay
Programmable output-current strength
Programmable slew rate
Programmable bus-hold
Programmable pull-up resistor
Programmable output delay
Open-drain output
R
R
R
Dynamic OCT for Arria II GZ devices
PCI clamping diode
S
D
T
Package
OCT
OCT for Arria II GZ devices
OCT
Table
6–6:
I/O
Clock
XVCR channel
I/O
Clock
XVCR channel
Pin Type
EP2AGZ225
550
726
16
24
4
8
Chapter 6: I/O Features in Arria II Devices
EP2AGZ300
(Note 1)
Device
December 2010 Altera Corporation
550
726
16
24
4
8
(Part 2 of 2)
EP2AGZ350
550
726
I/O Structure
16
24
4
8