EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 170

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–12
Figure 6–4. IOE Structure for Arria II GZ Devices
Notes to
(1) The D3_0 and D3_1 delays have the same available settings in the Quartus
(2) One dynamic OCT control is available per DQ/DQS group.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Firm Core
Figure
DQS
CQn
OE
from
Core
Write
Data
from
Core
clkout
To
Core
To
Core
Read
Data
to
Core
clkin
6–4:
4
f
4
D4 Delay
2
Rate Block
Half Data
Rate Block
Half Data
For more information about I/O registers and how they are used for memory
applications, refer to the
Rate Block
Half Data
D3_1
Delay
Output Register
Output Register
OE Register
OE Register
D
D
D
D
PRN
PRN
PRN
PRN
Q
Q
Q
Q
(Note
External Memory Interfaces in Arria II Devices
D3_0
Delay
Delay
1),
D1
(2)
Input Register
Input Register
D
D
PRN
PRN
D5, D6
Delay
Q
Q
®
D2 Delay
II software.
Programmable
Input Register
Strength and
D
Slew Rate
Current
Control
PRN
Q
Open Drain
D5, D6
Delay
Output Buffer
Input Buffer
Chapter 6: I/O Features in Arria II Devices
PCI Clamp
DQS Logic Block
December 2010 Altera Corporation
V CCIO
D5_OCT
Dynamic OCT Control (2)
V CCIO
Pull-Up Resistor
Programmable
Termination
chapter.
From OCT
Calibration
On-Chip
Bus-Hold
Block
D6_OCT
Circuit
I/O Structure