EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 427

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Receiver Channel Datapath
December 2010 Altera Corporation
Deskew FIFO
Use this module, only available in XAUI mode, to align all four channels to meet the
XAUI maximum skew of 40 UI (12.8 ns) as seen at the receiver of the four lanes. The
deskew operation in XAUI functional mode is compliant to the PCS deskew state
machine diagram specified in 8 of the IEEE P802.3ae.
The deskew circuitry consists of a 16-word deep deskew FIFO in each of the four
channels and control logic in the CMU0 channel of the transceiver block that controls
the deskew FIFO write and read operations in each channel.
deskew FIFO block diagram.
Figure 1–38. Deskew FIFO
Note to
(1) For more information about the deskew FIFO operation, refer to
Rate-Match FIFO
In asynchronous systems, you can clock the upstream transmitter and local receiver
with independent reference clocks. Frequency differences in the order of a few
hundred PPM can corrupt the data when latching from the recovered clock domain
(the same clock domain as the upstream transmitter reference clock) to the local
receiver reference clock domain.
The rate match FIFO compensates for small clock frequency differences between the
upstream transmitter and the local receiver clocks by inserting or removing SKP
symbols or ordered-sets from the IPG or idle streams. It deletes SKP symbols or
ordered-sets when the upstream transmitter reference clock frequency is higher than
the local receiver reference clock frequency. It inserts SKP symbols or ordered-sets
when the local receiver reference clock frequency is higher than the upstream
transmitter reference clock frequency.
The rate match FIFO consists of a 20-word deep FIFO and necessary logic that controls
insertion and deletion of a SKP character or ordered-set, depending on the PPM
difference. This module is optional in Basic functional mode, but is mandatory and
cannot be bypassed in GIGE, PCIe, and XAUI functional modes.
Figure 1–39
Figure 1–39. Rate Match FIFO
Note to
(1) These signals are not available in PCIe functional mode because the rate match FIFO status is encoded in the
pipestatus[2:0] signal.
Figure
Figure
1–38:
1–39:
shows the rate-match FIFO block diagram.
Data from either the Word
Aligner, Basic, GIGE,
and (PCIe, Functional Mode)
or the Deskew FIFO
(XAUI functional Mode)
Data from the Word Aligner
rx_syncstatus
(Note 1)
(20-Word Deep)
Deskew
Rate Match
FIFO
FIFO
“XAUI” on page
Arria II Device Handbook Volume 2: Transceivers
Data to the Rate-Match FIFO
rx_channelaligned
rx_rmfifodatainserted (1)
rx_rmfifodatadeleted (1)
rx_rmfifofull (1)
rx_fifoempty (1)
Figure 1–38
1–79.
shows the
1–41