EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 338

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–58
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Remote System Upgrade State Machine
1
Table 9–21
Table 9–21. Remote System Upgrade Status Register Contents
The remote system upgrade control and update registers have identical bit
definitions, but serve different roles (refer to
registers can only be updated when the device is loaded with a factory configuration
image, the update register writes are controlled by the user logic; the control register
writes are controlled by the remote system upgrade state machine.
In factory configurations, the user logic sends the AnF bit (set high), the page address,
and the watchdog timer settings for the next application configuration bit to the
update register. When the logic array configuration reset (RU_nCONFIG) goes low, the
remote system upgrade state machine updates the control register with the contents
of the update register and starts system reconfiguration from the new application
page.
To ensure successful reconfiguration between the pages, assert the RU_nCONFIG signal
for a minimum of 250 ns. This is equivalent to strobing the reconfig input of the
ALTREMOTE_UPDATE megafunction high for a minimum of 250 ns.
In the event of an error or reconfiguration trigger condition, the remote system
upgrade state machine directs the system to load a factory or application
configuration (page zero or page one, based on the mode and error condition) by
setting the control register accordingly.
register after such an event occurs for all possible error or trigger conditions.
The remote system upgrade status register is updated by the dedicated error
monitoring circuitry after an error condition but before the factory configuration is
loaded.
Table 9–22. Control Register Contents after an Error or Reconfiguration Trigger Condition
CRC (from the configuration)
nSTATUS
CORE_nCONFIG
nCONFIG
Wd
Note to
(1) Logic array reconfiguration forces the system to load the application configuration data into the Arria II device. This
(Part 1 of 2)
nCONFIG reset
nSTATUS error
CORE triggered reconfiguration
occurs after the factory configuration specifies the appropriate application configuration page address by updating
the update register.
Reconfiguration Error/Trigger
Status Register Bit
Table
lists the status register contents for remote system upgrade.
9–21:
(1)
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
CRC error caused reconfiguration
nSTATUS caused reconfiguration
Device logic array caused reconfiguration
nCONFIG caused reconfiguration
Watchdog timer caused reconfiguration
Table 9–22
Control Register Setting Remote Update
Definition
Figure 9–26 on page
lists the contents of the control
Dedicated Remote System Upgrade Circuitry
Update register
All bits are 0
All bits are 0
December 2010 Altera Corporation
9–56). While both
POR Reset Value
1 bit '0'
1 bit '0'
1 bit '0'
1 bit '0'
1 bit '0'