EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 576

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–2
Table 4–1. Reset, Power-Down, and Status Signals for Arria II Devices (Part 1 of 2)
Arria II Device Handbook Volume 2: Transceivers
Reset Signals For Each Transceiver Channel:
tx_digitalreset
rx_digitalreset
rx_analogreset
Power-Down Signal For Each CMU PLL in the Transceiver Block:
pll_powerdown
Power-Down Signal Common to the Transceiver Block:
gxb_powerdown
Status Signals:
pll_locked
rx_pll_locked
rx_freqlocked
Signal
(1)
(2)
(2)
(1)
Table 4–1
Provides asynchronous reset to all digital logic in the transmitter PCS, including the XAUI
transmit state machine, the built-in self test (BIST) pseudo-random binary sequence (PRBS)
generator, and the BIST pattern generator.
This signal is available in the ALTGX MegaWizard Plug-In Manager in Transmitter Only and
Receiver and Transmitter configurations. The minimum pulse width for this signal is two
parallel clock cycles.
Resets all digital logic in the receiver PCS, including the XAUI and GIGE receiver state
machine, the XAUI channel alignment state machine, the BIST-PRBS verifier, and the
BIST-incremental verifier.
This signal is available in the ALTGX MegaWizard Plug-In Manager in Receiver Only and
Receiver and Transmitter configurations. The minimum pulse width for this signal is two
parallel clock cycles.
Resets the receiver CDR present in the receiver channel.
This signal is available in the ALTGX MegaWizard Plug-In Manager in Receiver Only and
Receiver and Transmitter configurations. The minimum pulse width is two parallel clock
cycles.
Each transceiver block has two CMU PLLs. Each CMU PLL has a dedicated power-down signal
called pll_powerdown. The pll_powerdown signal powers down the CMU PLLs that provide
high-speed serial and low-speed parallel clocks to the transceiver channels.
Note: While each CMU PLL has its own pll_powerdown port, the ALTGX MegaWizard Plug-In
Manager instantiation provides only one port per transceiver block. This port power downs
one or both CMU PLLs (if used).
Powers down the entire transceiver block. When this signal is asserted, the PCS and PMA in
all the transceiver channels and the CMU PLLs are powered down. This signal operates
independently from the other reset signals
Indicates the status of the transmitter PLL. A high level on this signal indicates that the
transmitter PLL is locked to the incoming reference clock frequency.
A high level on this signal indicates that the receiver CDR is locked to the incoming reference
clock frequency.
Indicates the status of the receiver CDR lock mode. A high level indicates that the receiver is in
lock-to-data mode. A low level indicates that the receiver CDR is in lock-to-reference mode.
lists the available reset, power-down, and status signals.
Description
Chapter 4: Reset Control and Power Down in Arria II Devices
User Reset and Power-Down Signals
December 2010 Altera Corporation