EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 243

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Locations of the I/O Banks
Locations of the I/O Banks
Figure 8–1. High-Speed Differential I/Os with DPA Block Locations in an Arria II GX Device
Notes to
(1) This figure is a top view of the silicon die, which corresponds to a reverse view for flip chip packages. It is a graphical representation only.
(2) Applicable to EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
(3) There are no center PLLs on the right I/O banks for EP2AGX45 and EP2AGX65 devices.
December 2010 Altera Corporation
Figure
8–1:
Transceiver
Blocks
PLL
PLL
Arria II I/Os are divided into 16 to 20 I/O banks. For Arria II GX devices, the
high-speed differential I/O s are located at the right side of the device. For Arria II GZ
devices, the high-speed differential I/Os are located at the right and left sides of the
device.
Figure 8–1
and
High-Speed Differential I/O,
High-Speed Differential I/O,
and Memory Interface
General Purpose I/O,
and Memory Interface
General Purpose I/O,
Figure 8–2
Embedded Memory, and Clock Networks)
(Logic Elements, DSP,
show a high-level chip overview of Arria II devices.
FPGA Fabric
Arria II Device Handbook Volume 1: Device Interfaces and Integration
High-Speed Differential I/O,
High-Speed Differential I/O,
and Memory Interface
General Purpose I/O,
and Memory Interface
General Purpose I/O,
(Note
I/O with DPA,
I/O with DPA,
High-Speed
High-Speed
Differential
Differential
Purpose
Purpose
I/O, and
Memory
Interface
I/O, and
Memory
Interface
General
General
PLL
PLL
PLL
PLL
1), (2),
(3)
8–3