EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 307

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
PS Configuration
Figure 9–11. Multi-Device PS Configuration Using an External Host
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the Arria II device. For Arria II GX devices, use the V
(2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0]for an Arria II GX device, refer to
December 2010 Altera Corporation
For Arria II GZ devices, use the V
external host. Altera recommends powering up the configuration system I/Os with V
Table 9–6 on page
Figure
(MAX II Device or
Microprocessor)
External Host
ADDR
9–11:
Memory
9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to
DATA[0]
Figure 9–11
circuit is similar to the PS configuration circuit for a single device, except the Arria II
devices are cascaded for multi-device configuration.
In Arria II devices, the initialization clock source is either the internal oscillator or the
optional CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If you use the internal oscillator, the Arria II device provides itself with
enough clock cycles for proper initialization. Therefore, if the internal oscillator is the
initialization clock source, sending the entire configuration file to the device is
sufficient to configure and initialize the device. Driving DCLK to the device after
configuration is complete does not affect device operation.
You also have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II software from the
General tab of the Device and Pin Options dialog box. If you supply a clock on
CLKUSR, it does not affect the configuration process. Arria II devices support f
125 MHz.
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the second device’s nCE pin, which prompts the
second device to begin configuration. The second device in the chain begins
configuration in one clock cycle. Therefore, the transfer of data destinations is
transparent to the MAX II device or microprocessor. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to every device in the
chain. Configuration signals can require buffering to ensure signal integrity and
prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered for
every fourth device. Because all device CONF_DONE pins are tied together, all devices
initialize and enter user mode at the same time.
V
CCIO
CCPGM
/ V
(1)
CCPGM
pin. V
shows how to configure multiple devices using an external host. This
V
10 k Ω
CCIO
CCIO
/V
/ V
(1)
CCPGM
CCPGM
10 k Ω
GND
must be high enough to meet the V
DATA[0]
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
Arria II Device 1
Arria II Device Handbook Volume 1: Device Interfaces and Integration
MSEL[n..0]
nCEO
Table 9–7 on page
CCIO
V
/V
CCIO
(2)
CCPGM
IH
/ V
(1)
specification of the I/O on both the device and the
CCPGM
10 kΩ
.
9–10.
DATA[0]
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
Arria II Device 2
MSEL[n..0]
nCEO
MAX
N.C.
CCIO
of
(2)
9–27
pin.