EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 456

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–70
Table 1–19. Electrical Idle Inference Conditions for Arria II Devices (Part 1 of 2)
Arria II Device Handbook Volume 2: Transceivers
rx_elecidleinfersel[2:0]
3'b100
3'b101
3'b101
1
Fast Recovery Mode
The PCIe Base Specification fast training sequences (FTS) are used for bit and byte
synchronization to transition from L0s to L0 (PIPE P0s to P0) power states. The PCIe
specification requires the physical layer device to acquire bit and byte synchronization
after you transition from L0s to L0 state within 16 ns to 4 s.
If the Arria II GX and GZ receiver CDR is configured in Automatic Lock mode, the
receiver cannot meet the PCIe specification of acquiring bit and byte synchronization
within 4 s due to the signal detect and PPM detector time. To meet this specification,
each Arria II GX and GZ transceiver has built-in fast recovery circuitry that you can
optionally enable in the ALTGX MegaWizard Plug-In Manager with the Enable fast
recovery mode option.
Fast recovery circuitry controls the receiver CDR rx_locktorefclk and
rx_locktodata signals to force the receiver CDR in LTR or LTD modes, by relying on
the Electrical Idle Ordered Sets (EIOS), NFTS sequences received in L0 power state,
and the signal detect signal from the receiver input buffer to control the receiver CDR
lock mode. It is self-operational and does not require user inputs.
When you enable fast recovery mode, the rx_locktorefclk and rx_locktodata ports
are not available in the ALTGX MegaWizard Plug-In Manager.
Electrical Idle Inference
The PCIe protocol allows inferring the electrical idle condition at the receiver instead
of detecting the electrical idle condition using analog circuitry. PCIe Base Specification
2.0, section .2.4.3, specifies conditions to infer electrical idle at the receiver in various
sub-states of the LTSSM state machine.
In all PCIe modes (×1, ×4, and ×8), each receiver channel PCS has an optional
electrical idle inference module designed to implement the electrical idle inference
conditions specified in the PCIe Base Specification 2.0.
You can enable the electrical idle inference module by selecting the Enable electrical
idle inference functionality option in the ALTGX MegaWizard Plug-In Manager. This
feature infers electrical idle depending on the logic level driven on the
rx_elecidleinfersel[2:0] input signal. The electrical idle inference module drives
the pipeelecidle signal high in each receiver channel when an electrical idle
condition is inferred. For the electrical idle inference module to correctly infer an
electrical idle condition in each LTSSM substate, you must drive the
rx_elecidleinfersel[2:0] signal appropriately, as shown in
L0
Recovery.Speed when
successful speed
negotiation = 1'b1
Recovery.RcvrCfg
LTSSM State
Absence of TS1 or TS2 ordered set in 1280 UI interval
Absence of update FC or alternatively skip ordered set in 128 s
window
Absence of TS1 or TS2 ordered set in 1280 UI interval
Chapter 1: Transceiver Architecture in Arria II Devices
Description
December 2010 Altera Corporation
Table
1–19.
Functional Modes