EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 567

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Configuring Multiple Protocols and Data Rates in Arria II Devices
Combining Transmitter Channel and Receiver Channel Instances
Combining Transmitter Channel and Receiver Channel Instances
December 2010 Altera Corporation
Multiple Transmitter Channel and Receiver Channel Instances
You can create a separate transmitter channel instance and a separate receiver channel
instance and assign the tx_dataout and rx_datain pins of the transmitter and
receiver instance, respectively, in the same physical transceiver channel. This
configuration is useful in cases where you intend to run the transmitter and receiver
channel at different serial data rates. To create a transmitter channel instance and a
receiver channel instance, select the Transmitter Only and Receiver Only options in
the operating mode (General screen) of the ALTGX MegaWizard Plug-In Manager.
The Quartus II software allows you to combine multiple Transmitter Only channel
and Receiver Only channel instances within the same transceiver block. Based on the
pin assignments, the Quartus II software combines the corresponding Transmitter
Only and Receiver Only channels in the same physical channel. To enable the
Quartus II software to combine the transmitter channel and receiver channel instances
in the same transceiver block, follow the rules and requirements outlined in the
following sections:
■
■
■
■
Example 3
Consider that you create four ALTGX instances, as shown in
Table 3–4. Four ALTGX Instances for Example 3 for Arria II Devices
After you create the above instances, if you force the placement of the instances
shown in
channel 0 and inst2 and inst3 into physical channel 1.
Table 3–5. Forced Placement of the Instances for Example 3 for Arria II Devices
inst0
inst1
inst2
inst3
inst0
inst1
inst2
inst3
“General Requirements to Combine Channels” on page 3–2
“Multiple Channels Sharing a CMU PLL” on page 3–3
“Multiple Channels Sharing Two CMU PLLs” on page 3–6
“Combining Receiver Only Channels” on page 3–8
Instance Name
Instance Name
Table
3–5, the Quartus II software combines inst0 and inst1 into physical
Physical Channel Pin Assignments in the Same Transceiver Block
Transmitter only
Transmitter only
Configuration
Receiver only
Receiver only
Effective Data Rate
RX pin of channel 0
RX pin of channel 1
TX pin of channel 0
TX pin of channel 1
Arria II Device Handbook Volume 2: Transceivers
(Gbps)
3.125
1.25
2.5
2
Table
3–4.
Clock Frequency
Input Reference
156.25
156.25
(MHz)
125
125
3–9