EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 431

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Receiver Channel Datapath
Figure 1–45. Example of Byte Ordering Operation
December 2010 Altera Corporation
tx_datain[15:8]
tx_datain[7:0]
D2
D1
D3
A
Transmitter
D5
D4
The byte ordering modules have two different modes of operation when you select
the rx_syncstatus signal from the word aligner option in the What do you want the
byte ordering to be based on? field in the ALTGX MegaWizard Plug-In Manager:
■
■
Word-Alignment-Based Byte Ordering—In this mode, the byte ordering block
starts looking for the byte ordering pattern in the byte-deserialized data every
time it sees a rising edge on the rx_syncstatus signal.
User-Controlled Byte Ordering—Unlike word-alignment-based byte ordering,
user-controlled byte ordering provides control to the user logic to restore correct
byte ordering at the receiver.
If the byte ordering block finds the first data byte that matches the programmed
byte ordering pattern in the MSByte position of the byte-deserialized data, it
inserts one programmed PAD pattern to push the byte ordering pattern into the
LSByte position after a rising edge on the rx_syncstatus signal.
If the byte ordering blocks finds the first data byte that matches the programmed
byte ordering pattern in the LSByte position of the byte-deserialized data, it
considers the data to be ordered and does not insert any PAD pattern. In either
case, the byte ordering block asserts the rx_byteorderalignstatus signal.
Figure 1–45
programmed byte ordering pattern and PAD is the programmed PAD pattern. The
byte deserialized data places the byte ordering pattern A in the MSByte position,
resulting in incorrect byte ordering. Assuming that a rising edge on the
rx_syncstatus signal had occurred before the byte ordering block sees the byte
ordering pattern A in the MSByte position, the byte ordering block inserts a PAD
byte and pushes the byte ordering pattern A into the LSByte position. The data at
the output of the byte ordering block has correct byte ordering as reflected on the
rx_byteorderalignstatus signal.
If the byte ordering block sees another rising edge on the rx_syncstatus signal
from the word aligner, it de-asserts the rx_byteorderalignstatus signal and
repeats the byte ordering operation.
When enabled, an rx_enabyteord port is available as a trigger to the byte ordering
operation. A rising edge on the rx_enabyteord port triggers the byte ordering
block. If the byte ordering block finds the first data byte that matches the
programmed byte ordering pattern in the MSByte position of the byte-deserialized
data, it inserts one programmed PAD pattern to push the byte ordering pattern
Serializer
Byte
Channel
shows an example of the byte ordering operation where A is the
Deserializer
Byte
Receiver
D1
XX
D2
A
D4
D3
Ordering
Byte
Arria II Device Handbook Volume 2: Transceivers
rx_byteorderalignstatus
XX
D1
PAD
D2
D3
A
D5
D4
rx_dataout[15:8]
rx_dataout[7:0]
1–45