EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 54

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–8
Figure 3–7. Output Latch Asynchronous Clear Waveform
Arria II Device Handbook Volume 1: Device Interfaces and Integration
aclr at latch
Mixed Width Support
Asynchronous Clear
Error Correction Code Support
outclk
aclr
f
1
q
M9K and M144K blocks support mixed data widths inherently. MLABs can support
mixed data widths through emulation with the Quartus II software. When using
simple dual-port, true dual-port, or FIFO modes, mixed width support allows you to
read and write different data widths to a memory block. For more information about
the different widths supported per memory mode, refer to
page
MLABs do not support mixed-width FIFO mode.
Arria II memory blocks support asynchronous clears on the output latches and output
registers. Therefore, if your RAM is not using output registers, you can still clear the
RAM outputs using the output latch asynchronous clear.
functional waveform showing this functionality.
You can selectively enable asynchronous clears per logical memory using the RAM
MegaWizard Plug-In Manager.
For more information about the RAM MegaWizard Plug-In Manager, refer to the
Internal Memory (RAM and ROM) Megafunction User
Arria II GZ M144K blocks have built-in support for ECC when in ×64-wide simple
dual-port mode. ECC allows you to detect and correct data errors in the memory
array. The M144K blocks have a single-error-correction double-error-detection
(SECDED) implementation. SECDED can detect and fix a single bit error in a 64-bit
word, or detect two bit errors in a 64-bit word. It cannot detect three or more errors.
The M144K ECC status is communicated using a three-bit status flag
(eccstatus[2..0]). The status flag can be either registered or unregistered. When
registered, it uses the same clock and asynchronous clear signals as the output
registers. When unregistered, it cannot be asynchronously cleared.
3–10.
Chapter 3: Memory Blocks in Arria II Devices
Guide.
Figure 3–7
“Memory Modes” on
December 2010 Altera Corporation
shows a
Memory Features