EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 238

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–42
Document Revision History
Table 7–11. Document Revision History (Part 1 of 2)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
July 2010
November 2009
June 2009
Date
Version
For Arria II GZ devices, the output path is designed to route combinatorial or
registered SDR outputs and full-rate or half-rate DDR outputs from the FPGA core.
Half-rate data is converted to full-rate using the HDR block, clocked by the half-rate
clock from the PLL.
The output-enable path has a structure similar to the output path. You can have a
combinatorial or registered output in SDR applications and you can use half-rate or
full-rate operation in DDR applications. Also, the ouput-enable path’s
resynchronization registers have a structure similar to the output path registers,
ensuring that the output-enable path goes through the same delay and latency as the
output path.
Table 7–11
4.0
2.0
3.0
1.2
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Updated for Arria II GX v10.0 release:
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Updated for Arria II GX v9.1 release:
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Updated for the Quartus II software version 10.1 release.
Added Arria II GZ devices information.
Added
Figure
Added
Table
Updated
Added
Arria II GZ Devices”
Minor text edits.
Updated “Arria II Memory Interfaces Pin Support” section by adding reference to the
Section I. Device and Pin Planning in volume 2 of the External Memory Interface
Handbook and removing “Table 7–1: Memory Interface Pin Utilization”.
Update DLL numbering to match with the Quartus II software.
Minor text edits.
Updated Table 7–1, Table 7–2, and Table 7–5.
Updated Figure 7–1, Figure 7–2, Figure 7–3, Figure 7–11, Figure 7–12, Figure 7–13,
Figure 7–15, and Figure 7–16.
Updated the “Arria II GX External Memory Interface Features” section.
Added new “Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM
Interface” section.
Minor text edits.
Added Table 7–2.
Updated Table 7–1, Table 7–3, and Table 7–5.
Updated Figure 7–1, Figure 7–3, Figure 7–4, Figure 7–5, Figure 7–6, Figure 7–7,
Figure 7–8, Figure 7–9, and Figure 7–11.
Updated “Introduction” and “DLL” sections.
shows the revision history for this document.
7–7,
7–15,
Figure
Table
“Using the R
Table
Table
7–1,
Figure
7–2,
7–10.
7–8, and
Table
Figure
UP
7–17,
and
and R
7–3,
“Arria II GZ Dynamic On-Chip Termination Control”
7–10,
Table
Figure
DN
Table
Pins in a DQ/DQS Group Used for Memory Interfaces in
Figure
7–9.
7–19,
7–4,
Changes
7–11,
Chapter 7: External Memory Interfaces in Arria II Devices
Figure
Table
Figure
7–5,
7–24,
Table
7–12,
Figure
7–3,
Figure
December 2010 Altera Corporation
7–26, and
Table
7–13,
Document Revision History
7–4,
Figure
Figure
Table
sections.
7–26.
7–6,
7–14,