EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 584

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–10
Arria II Device Handbook Volume 2: Transceivers
1
As shown in
CDR in manual lock mode configuration:
1. After power up, assert pll_powerdown for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high
4. Wait for the rx_pll_locked signal from each channel to go high. The
5. In a bonded channel group, when the last rx_pll_locked signal goes high, from
6. De-assert rx_digitalreset at least 4 s (the time between markers 8 and 9) after
Non-Bonded Channel Configuration
In non-bonded channels, each channel in the ALTGX megafunction instance contains
its own tx_digitalreset, rx_analogreset, rx_digitalreset, rx_pll_locked, and
rx_freqlocked signals.
You can reset each channel independently. For example, if there are four non-bonded
channels, the ALTGX MegaWizard Plug-In Manager provides five signals:
tx_digitalreset, rx_analogreset, rx_digitalreset, rx_pll_locked, and
rx_freqlocked.
The following timing diagrams describe the reset and power-down sequences for one
channel in a non-bonded configuration, under five different setups:
■
■
■
■
■
Follow the same reset sequence for all the other channels in the non-bonded
configuration.
between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted
during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
(marker 3), de-assert the tx_digitalreset signal (marker 4). For the receiver
operation, after de-assertion of the busy signal, wait for two parallel clock cycles to
de-assert the rx_analogreset signal. After the rx_analogreset signal is de-
asserted, the receiver CDR of each channel starts locking to the receiver input
reference clock because rx_locktorefclk is asserted.
rx_pll_locked signal of each channel may go high at different times with respect
to each other (indicated by the slashed pattern at the marker 7).
that point onwards, wait at least 15 s and then de-assert rx_locktorefclk and
assert rx_locktodata (marker 8). At this point, the receiver CDR enters
lock-to-data mode and the receiver PLL starts locking to the received data.
asserting the rx_locktodata signal.
Transmitter Only channel setup
Receiver Only channel setup—receiver CDR in automatic lock mode
Receiver Only channel setup—receiver CDR in manual lock mode
Receiver and Transmitter channel setup—receiver CDR in automatic lock mode
Receiver and Transmitter channel setup—receiver CDR in manual lock mode
Figure
4–5, perform the following reset sequence steps for the receiver
Chapter 4: Reset Control and Power Down in Arria II Devices
December 2010 Altera Corporation
Transceiver Reset Sequences