EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 402

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–16
Figure 1–17. 8B/10B Encoder Output during tx_digitalreset Assertion
Arria II Device Handbook Volume 2: Transceivers
tx_digitalreset
dataout[9:0]
clock
1
K28.5-
Figure 1–16
can, however, enable the Transmitter Bit Reversal option in the ALTGX MegaWizard
Plug-In Manager to allow reversing the transmit bit order (MSB first) before it is
forwarded to the serializer.
Figure 1–16. 8B/10B Conversion Format
During reset, the running disparity and data registers are cleared. Also, the 8B/10B
encoder outputs a K28.5 pattern from the RD- column continuously until
tx_digitalreset is de-asserted. The input data and control code from the FPGA
fabric is ignored during the reset state. After power up or reset, the 8B/10B encoder
starts with a negative disparity (RD-) and transmits three K28.5 code groups for
synchronization before it starts encoding and transmitting data on its output.
While tx_digitalreset is asserted, the downstream 8B/10B decoder that receives the
data might observe synchronization or disparity errors.
Figure 1–17
(tx_digitalreset is high), a K28.5- (K28.5 10-bit code group from the RD- column) is
sent continuously until tx_digitalreset is low. Due to some pipelining of the
transmitter channel PCS, some “don’t cares” (10'hxxx) are sent before the three
synchronizing K28.5 code groups. User data follows the third K28.5 code group.
In Basic functional mode, you can use the tx_forcedisp and tx_dispval ports to
control the running disparity of the output from the 8B/10B encoder. Forcing
disparity can either maintain the current running disparity calculations if the forced
disparity value (on the tx_dispval bit) happens to match the current running
disparity, or flip the current running disparity calculations if it does not match. If the
forced disparity flips the current running disparity, the downstream 8B/10B decoder
might detect a disparity error.
K28.5-
shows the conversion format. The LSB is transmitted first by default. You
shows the reset behavior of the 8B/10B encoder. When in reset
K28.5-
XXX
Default Operation (Transmitter Bit Reversal Disabled)
MSB
LSB
H
7 6 5 4 3 2 1 0
Transmitter Bit Reversal Enabled
a
0
G
9 8
j
1
b
F
h
2
c d e i
E
8B/10B Encoder
g
7 6 5 4 3 2 1 0
3
D
f
XXX
4
C
i
5
B
e
Chapter 1: Transceiver Architecture in Arria II Devices
6
f g
A
d
7
control_bit
c
K28.5-
8
h j
b a
9
MSB
LSB
K28.5+
December 2010 Altera Corporation
Transmitter Channel Datapath
K28.5-
Dx.y+