EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 499

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
Table 2–2. Transmitter Channel Datapath Clock Frequencies in Non-Bonded Functional Modes for Arria II Devices
December 2010 Altera Corporation
Note to
(1) 250 MHz when you enable the PCIe hard IP.
(2) Altera also supports CPRI and OBSAI. For more information, refer to
Functional Mode
SONET/SDH OC12
SONET/SDH OC48
PCIe ×1 (Gen 1)
PCIe ×1 (Gen 2)
Serial RapidIO
Table
HD-SDI
3G-SDI
GIGE
2–2:
(2)
In non-bonded channel configurations, each channel can derive its clock
independently from either CMU0 PLL or CMU1 PLL within the same transceiver block.
The CMU PLL synthesizes the input reference clock to generate a clock that runs at a
frequency of half the configured data rate. This half-rate clock from the CMU PLL is
fed to the local clock divider block in each channel. Depending on the configured
functional mode, the local clock divider block in each channel generates the
low-speed parallel clock and high-speed serial clock. The serializer in the transmitter
channel PMA uses both the low-speed parallel clock and high-speed serial clock for
its parallel-in, serial-out operation. The low-speed parallel clock clocks both the
8B/10B encoder (if enabled) and the read port of the byte serializer (if enabled) in the
transmitter channel PCS.
If the configured functional mode does not use the byte serializer, the low-speed
parallel clock provides a clock to the read port of the transmitter phase compensation
FIFO. The low-speed parallel clock is also driven directly on the tx_clkout port as the
FPGA fabric-transceiver interface clock. You can use the tx_clkout port to clock
transmitter data and control logic in the FPGA fabric.
If the configured functional mode uses a byte serializer to reduce the FPGA
fabric-transceiver interface speed, the low-speed parallel clock is divided by two. This
divide-by-two version of the low-speed parallel clock provides a clock to the write
port of the byte serializer and the read port of the transmitter phase compensation
FIFO. It is also driven on the tx_clkout port as the FPGA fabric-transceiver interface
clock. You can use tx_clkout to clock transmitter data and control logic in the FPGA
fabric.
Table 2–2
functional modes that have a fixed data rate.
1.4835 Gbps
3.125 Gbps
2.488 Gbps
1.485 Gbps
2.967 Gbps
1.25 Gbps
1.25 Gbps
2.97 Gbps
Data Rate
622 Mbps
2.5 Gbps
2.5 Gbps
5 Gbps
lists the transmitter channel datapath clock frequencies in non-bonded
Serial Clock
741.75 MHz
High-Speed
1.5625 GHz
1.4835 GHz
Frequency
742.5 MHz
1.244 GHz
1.485 GHz
1.25 GHz
1.25 GHz
625 MHz
625 MHz
311 MHz
2.5 GHz
AN 610: Implementing CPRI and OBSAI Protocols in Altera
Parallel Clock
Low-Speed
Frequency
148.35
(MHz)
312.5
77.75
148.5
296.7
250
500
125
125
250
311
297
Arria II Device Handbook Volume 2: Transceivers
Serializer (MHz)
FPGA Fabric-Transceiver Interface
Without Byte
250
148.35
77.75
148.5
125
—
—
—
—
—
—
—
(1)
Clock Frequency
Serializer (MHz)
With Byte
156.25
74.175
148.35
155.5
74.25
148.5
62.5
125
250
125
Devices.
—
—
2–9