EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 463

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Figure 1–73. SONET/SDH OC-48 Datapath
Figure 1–74. SONET/SDH OC-96 Datapath
December 2010 Altera Corporation
tx_coreclk
tx_coreclk
rx_coreclk
rx_coreclk
FPGA
Fabric
FPGA
Fabric
FPGA Fabric-Transmitter
FPGA Fabric-Transmitter
SONET/SDH OC-48 Datapath
Figure 1–73
mode.
SONET/SDH OC-96 Datapath
Figure 1–74
mode.
FPGA Fabric-Receiver
FPGA Fabric-Receiver
Interface Clock
Interface Clock
Interface Clock
Interface Clock
shows the transceiver datapath when configured in SONET/SDH OC-48
shows the transceiver datapath when configured in SONET/SDH OC-96
tx_clkout
rx_clkout
tx_clkout
rx_clkout
Compensation
Compensation
RX Phase
RX Phase
FIFO
FIFO
Compensation
Compensation
wrclk
wrclk
TX Phase
TX Phase
FIFO
FIFO
rdclk
rdclk
Ordering
Byte
wrclk
wrclk
Serializer
Serializer
Transmitter Channel PCS
Transmitter Channel PCS
Byte De-
serializer
Byte De-
serializer
Byte
Byte
/2
/2
/2
/2
Low-Speed Parallel Clock
Receiver Channel PCS
Low-Speed Parallel Clock
Receiver Channel PCS
rdclk
rdclk
Recovered Clock
Recovered Clock
Parallel
Parallel
Aligner
Aligner
Word
Word
Arria II Device Handbook Volume 2: Transceivers
Receiver Channel PMA
Receiver Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Serializer
Serializer
De-
De-
Serializer
Serializer
Divider
Divider
Clock
Clock
Local
Local
CDR
CDR
High-Speed
Serial Clock
High-Speed
Serial Clock
1–77