EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 310

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–30
Table 9–12. PS Timing Parameters for Arria II Devices (Part 2 of 2)—Preliminary
Arria II Device Handbook Volume 1: Device Interfaces and Integration
f
t
t
t
t
t
Notes to
(1) This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
(2) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
MAX
R
CD2UM
CD2CU
CD2UMC
Symbol
Table
PS Configuration Using a Download Cable
DCLK frequency
Input rise time
Input fall time
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
9–12:
f
1
For more information about device configuration options and how to create
configuration files, refer to the
Formats
In this section, the generic term “download cable” includes the Altera USB-Blaster
USB port download cable, ByteBlaster II parallel port download cable,
ByteBlasterMV
EthernetBlaster II download cable.
In a PS configuration with a download cable, an intelligent host (such as a PC)
transfers data from a storage device to the Arria II device using the download cable.
During configuration, the programming hardware or download cable places the
configuration data one bit at a time on the device’s DATA0 pin. The configuration data
is clocked into the target device until CONF_DONE goes high.
When using a download cable, setting the Auto-restart configuration after error
option does not affect the configuration cycle because you must manually restart the
configuration in the Quartus II software when an error occurs. Additionally, the
Enable user-supplied start-up clock (CLKUSR) option has no affect on the device
initialization because this option is disabled in the .sof when programming the device
using the Quartus II programmer and download cable. Therefore, if you turn on the
CLKUSR option, you are not required to provide a clock on the CLKUSR pin when you
are configuring the device with the Quartus II programmer and a download cable.
chapters in volume 2 of the Configuration Handbook.
Parameter
TM
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
(3)
parallel port download cable, EthernetBlaster download cable, and
Device Configuration Options
CLKUSR period)
t
4 × maximum
CD2CU
DCLK period
Minimum
—
—
—
55
+ (8532
and
December 2010 Altera Corporation
Maximum
125
150
40
40
—
—
Configuration File
PS Configuration
Units
MHz
—
—
ns
ns
ns