EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 202

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–6
Table 7–2. Number of DQ/DQS Groups and I/O Modules per Side in Arria II GX Devices
Table 7–3. Number of DQ/DQS Groups per Side in Arria II GZ Devices (Part 1 of 2)—Preliminary
Arria II Device Handbook Volume 1: Device Interfaces and Integration
EP2AGX45
EP2AGX65
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
Note to
(1) Each I/O module consists of 16 I/O pins. 12 of the 16 pins are DQ/DQS pins.
EP2AGZ300
EP2AGZ350
EPAGZ225
EP2AGZ300
EP2AGZ350
Device
Device
Table
7–2:
f
358-Pin Ultra
FineLine BGA
572-Pin
FineLine BGA
780-Pin
FineLine BGA
1152-Pin
FineLine BGA
1152-Pin
FineLine BGA
Package
780-pin
FineLine BGA
1152-pin
FineLine BGA
1152-pin
FineLine BGA
Package
Table 7–2
Arria II GX device. For a more detailed listing of the number of DQ/DQS groups
available per bank in each Arria II GX device, refer to
Figure 7–10 on page
device.
For more information about DQ/DQS groups pin-out restriction format, refer to the
Arria II Device Family Pin Connection
Table 7–3
device. For a more detailed listing of the number of DQ/DQS groups available per
bank in each Arria II GZ device, refer to
figures represent the die top view of the Arria II GZ device.
Top/Bottom/
Top/Bottom/
Top/Bottom
Top/Bottom
Top/Bottom
lists the number of I/O modules and DQ/DQS groups per side of the
lists the number of DQ/DQS groups available per side in each Arria II GZ
Right
Right
Right
Right
Right
Side
Top/Bottom
Top/Bottom
Top/Bottom
Left/Right
Left/Right
Left/Right
Side
7–13. These figures represent the die top view of the Arria II GX
Number of I/O
Module
12
×4
3
2
4
6
7
9
8
18
13
26
13
26
0
(1)
(1)
Number of DQ/DQS Groups
Guidelines.
×8/×9
12
12
×4
12
14
18
16
24
0
8
6
6
6
4
8
Figure 7–11
Number of DQ/DQS Groups
Chapter 7: External Memory Interfaces in Arria II Devices
×8/×9
×16/×18
12
3
2
4
6
7
9
8
Memory Interfaces Pin Support for Arria II Devices
2
0
2
2
4
4
through
Figure 7–4 on page 7–7
×16/×18
1
0
2
2
3
4
4
6
×32/×36
December 2010 Altera Corporation
Figure
2
0
0
0
0
0
×32/×36
(3)
0
0
0
0
1
2
2
2
(2)
7–15. These
Figure 7–11 on
page 7–14
Figure 7–12 on
page 7–15
Figure 7–13 on
page 7–16
Figure 7–4 on
page 7–7
Figure 7–5 on
page 7–8
Figure 7–6 on
page 7–9
Figure 7–7 on
page 7–10
Figure 7–8 on
page 7–11
Figure 7–9 on
page 7–12
Figure 7–10
on page 7–13
Refer to
Refer to
through