EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 366

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

11–6
Table 11–3. Supported TDO/TDI Voltage Combinations for Arria II GX Devices (Part 2 of 2)
Table 11–4. Supported TDO/TDI Voltage Combinations for Arria II GZ Devices
Disabling IEEE Std. 1149.1 BST Circuitry
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Non-Arria II GX
Notes to
(1) The TDO output buffer meets V
(2) The TDO output buffer meets V
(3) An external 250-Ω pull-up resistor is not required; however, they are recommended if signal levels on the board are not optimal.
(4) The input buffer must be 3.0-V tolerant.
(5) The input buffer must be 2.5-V tolerant.
(6) The input buffer must be 1.8-V tolerant.
Notes to
(1) The TDO output buffer meets V
(2) The TDO output buffer meets V
(3) The input buffer must be 3.0-V tolerant.
(4) The input buffer must be 2.5-V tolerant.
Non-Arria II GZ
Arria II GZ
Device
Device
Table
Table
11–3:
11–4:
f
TDI Input Buffer
For more information about I/O voltage support in the JTAG chain, refer to the “ I/O
Voltage Support in JTAG Chain” in the
Arria GX Devices
The IEEE Std. 1149.1 BST circuitry for Arria II devices is enabled after device
power up. Because the IEEE Std. 1149.1 BST circuitry is used for BST or in-circuit
reconfiguration, you must enable the circuitry only at specific times as mentioned in
“IEEE Std. 1149.1 BST Circuitry” in the
Arria GX Devices
TDI Input Buffer Power
V
V
V
V
CC
CC
CC
CC
Power
= 3.3 V
= 2.5 V
= 1.8 V
= 1.5 V
V
V
OH
OH
OH
OH
V
V
V
V
CCPD
CCPD
(Min) = 2.4 V.
(Min) = 2.0 V.
CC
CC
CC
CC
(Min) = 2.4 V.
(Min) = 2.0 V.
= 3.3 V
= 2.5 V
= 1.8 V
= 1.5 V
= 3.0 V
= 2.5 V
V
chapter in volume 2 of the Arria GX Device Handbook.
chapter in volume 2 of the Arria GX Device Handbook.
CCIO
v
v
v
= 3.3 V
v
(4)
(4)
(4)
(1)
V
Arria II GX TDO V
V
CC
Arria II GZ TDO V
CCIO
PD
v
v
v
= 3.0 V
v
v
v
= 3.0 V
v
v
v
v
IEEE 1149.1 (JTAG) Boundary-Scan Testing for
(3)
(3)
(3)
IEEE 1149.1 (JTAG) Boundary-Scan Testing for
(4)
(4)
(4)
Chapter 11: JTAG Boundary-Scan Testing in Arria II Devices
(1)
(1)
CCIO
CCPD
V
CCIO
Voltage Level in I/O Bank 8C
Voltage Level in I/O Bank 1A
v
v
= 2.5 V
v
v
(5)
(5)
Disabling IEEE Std. 1149.1 BST Circuitry
December 2010 Altera Corporation
(2)
V
CC
V
PD
CCIO
v
v
= 2.5 V
v
v
v
v
v
v
v
v
= 1.8 V
(4)
(4)
(3)
(3)
(6)
(2)
V
Level shifter
Level shifter
Level shifter
CCIO
required
required
required
v
= 1.5 V