EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 43

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Adaptive Logic Modules
Figure 2–12. LUT Register from Two Combinational Blocks
Figure 2–13. ALM in LUT-Register Mode with 3-Register Capability
December 2010 Altera Corporation
datain(datac)
aclr
sclr
clk
DC1
E0
E1
F1
F0
LUT-Register Mode
LUT-Register mode allows third register capability in an ALM. Two internal feedback
loops allow combinational ALUT1 to implement the master latch and combinational
ALUT0 to implement the slave latch needed for the third register. The LUT register
shares its clock, clock enable, and asynchronous clear sources with the top dedicated
register.
the ALM.
Figure 2–13
clk [2..0] aclr [1..0]
Figure 2–12
shows the ALM in LUT-Register mode.
shows the register constructed using two combinational blocks in
datain
aclr
sclr
Third register
latchout
regout
reg_chain_in
Arria II Device Handbook Volume 1: Device Interfaces and Integration
reg_chain_out
datain
sdata
datain
sdata
4-input
5-input
aclr
aclr
LUT
LUT
regout
regout
Master latch
Slave latch
combout
combout
sumout
sumout
lelocal 1
leout 1 a
leout 1 b
lelocal 0
leout 0 b
leout 0 a
LUT regout
2–15