EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 465

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Figure 1–75. SONET/SDH OC-48 Byte Ordering Example
December 2010 Altera Corporation
From Byte Deserializer
XAUI
rx_syncstatus
1
rx_dataout
rx_dataout
rx_clkout
(MSB)
(LSB)
The OC-96 byte serializer converts 32-bit data words from the FPGA fabric and
translates them into two 16-bit data words at twice the rate. The OC-96 byte
deserializer takes in two consecutive 16-bit data words and translates them into a
32-bit data word to the FPGA fabric at half the rate.
Byte Ordering in SONET/SDH OC-48 Mode
Because of byte deserialization, the MSByte of a word might appear at the rx_dataout
port along with the LSByte of the next word. In a SONET/SDH OC-48 configuration,
you can use the byte ordering block that is built into the datapath to perform byte
ordering. Byte ordering in a SONET/SDH OC-48 configuration is in word
alignment-based mode, where the byte ordering block is triggered by the rising edge
of the rx_syncstatus signal.
At the rising edge of the rx_syncstatus signal, the byte ordering block compares the
LSByte coming out of the byte deserializer with the A2 byte of the A1A2 alignment
pattern. If the LSByte coming out of the byte deserializer does not match the A2 byte
set in the ALTGX MegaWizard Plug-In Manager, the byte ordering block inserts a
PAD character, as shown in
ordering block to restore the correct byte order.
The PAD character is defaulted to the A1 byte of the A1A2 alignment pattern.
Use this functional mode for XAUI, HiGig, or HiGig+ protocols.
The XAUI is an optional, self-managed interface that you can insert between the
reconciliation sublayer and the PHY layer to transparently extend the physical reach
of the XGMII.
A1
X
A1
A1
A2
A1
A2
A2
D0
A2
Figure
D2
D1
rx_byteorderalignstatus
1–75. Inserting this PAD character enables the byte
Ordering
Block
rx_syncstatus
Byte
A1
X
Arria II Device Handbook Volume 2: Transceivers
A1
A1
Pad
A1
To PLD Core
A2
A2
D1
D0
D3
D2
1–79