EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 588
EP2AGX190EF29I5N
Manufacturer Part Number
EP2AGX190EF29I5N
Description
IC ARRIA II GX FPGA 190K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190EF29I5N.pdf
(306 pages)
Specifications of EP2AGX190EF29I5N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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4–14
Figure 4–9. Sample Reset Sequence of Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
Arria II Device Handbook Volume 2: Transceivers
Reset Signals
CDR Control Signals
Output Status Signals
pll_powerdown
rx_analogreset
tx_digitalreset
rx_digitalreset
rx_locktorefclk
rx_pll_locked
rx_locktodata
pll_locked
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. If you create a
Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with
the receiver CDR in manual lock mode, use the reset sequence shown in
As shown in
manual lock mode:
1. After power up, assert pll_powerdown for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high
busy
between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted
during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
(marker 3), de-assert tx_digitalreset. For receiver operation, wait for the busy
signal to be de-asserted. At this point, rx_analogreset is de-asserted. After
rx_analogreset is de-asserted, the receiver CDR starts locking to the receiver
input reference clock because rx_locktorefclk is asserted.
1
1 μs
Figure
2
4–9, perform the following reset sequence steps for the receiver in
3
Two parallel clock cycles
4
5
6
7
Chapter 4: Reset Control and Power Down in Arria II Devices
15 μs
8
8
4 μs
9
December 2010 Altera Corporation
Transceiver Reset Sequences
Figure
4–9.
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