EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 394

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–8
Figure 1–5. CMU0 Block Diagram
Notes to
(1) Although each CMU PLL has its own pll_powerdown port, the ALTGX MegaWizard Plug-In Manager instantiation provides only one port per
(2) The inter-transceiver block (ITB) clock lines shown are the maximum value. The actual number of ITB lines in your device depends on the number
(3) There is one pll_locked signal per CMU PLL.
(4) Used in ×4, ×8, and XAUI functional modes. In ×8 functional mode, only the CMU0 channel of the master transceiver block provides clock output
Figure 1–6. CMU1 Block Diagram
Notes to
(1) Although each CMU PLL has its own pll_powerdown port, the ALTGX MegaWizard Plug-In Manager instantiation provides only one port per
(2) The ITB clock lines shown are the maximum value. The actual number of ITB lines in your device depends on the number of transceiver blocks
(3) There is one pll_locked signal per CMU PLL.
Arria II Device Handbook Volume 2: Transceivers
CMU1 PLL High-Speed Clock
transceiver block. This port power downs one or both CMU PLLs (if used).
of transceiver blocks on one side of the device.
to all eight transceiver channels configured in PCIe functional mode.
transceiver block. This port power downs one or both CMU PLLs (if used).
on one side of the device.
PLL Cascade Clock
Figure
Figure
ITB Clock Lines (2)
pll_powerdown (1)
Global Clock Line
Dedicated refclk0
Dedicated refclk1
PLL Cascade Clock
ITB Clock Lines (2)
pll_powerdown (1)
Global Clock Line
Dedicated refclk0
Dedicated refclk1
1–5:
1–6:
Figure 1–5
respectively.
6
CMU0 Block
6
CMU1 Block
and
Input Reference Clock
Figure 1–6
CMU0 PLL
Input Reference
CMU1 PLL
Clock
show the top-level block diagram of CMU0 and CMU1 blocks,
CMU0 PLL
CMU1 PLL
CMU0 PLL High-Speed
Clock for Non-Bonded Modes
Clock for Non-Bonded Modes
CMU1 PLL High-Speed
CMU0 Clock
Chapter 1: Transceiver Architecture in Arria II Devices
Divider
for Bonded Modes
High-Speed Serial
Clock for Bonded
Parallel Clock
Low-Speed
Modes (4)
December 2010 Altera Corporation
Clock Multiplier Units (CMU)
pll_locked (3)
To Transmitter
Channel Local
Clock Divider
(4)
To Transmitter Channel
To PCS Blocks
pll_locked (3)
Local Clock Divider