EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 397

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Transceiver Channel Architecture
Transceiver Channel Architecture
Figure 1–10. Transceiver Channel Architecture for Arria II GX and GZ Devices
Notes to
(1) Shaded boxes are in the FPGA; unshaded boxes are in the I/O periphery.
(2) The PCIe hard IP block and PIPE interface are used only when the FPGA design includes the PCIe megafunction. For more information about the
December 2010 Altera Corporation
Fabric
FPGA
use of these two blocks, refer to the
Figure
1–10:
FPGA-to-Fabric Interface (2)
Each transceiver channel consists of a transmitter channel and a receiver channel.
Each transmitter or receiver channel comprises the channel PCS and channel PMA
blocks.
The FPGA fabric-to-transceiver interface and the PMA-to-PCS interface can support
an 8, 10, 16, or 20 bit-width data bus.
The transceiver channel is available in two modes:
■
■
Single-width mode—In this mode, the PMA-to-PCS interface uses an 8- or 10-bit
wide data bus. The FPGA fabric-to-transceiver interface supports an 8- or 10-bit
wide data bus, with the byte serializer/deserializer disabled. When the byte
serializer/deserializer is enabled, the FPGA fabric-to-transceiver interface
supports a 16 or 20 bit-width data bus.
Double-width mode—In this mode, both the PMA-to-PCS interface and the FPGA
fabric-to-transceiver uses an 16- and 20-bit wide data bus. The byte
serializer/deserializer is supported in Arria II GZ devices, but not in Arria II GX
devices. This mode is only supported for BASIC or Deterministic Latency protocol,
used for CPRI and OBSAI interfaces.
Figure 1–10
PCI Express Compiler User
wrclk
tx_clkout
rdclk
shows the Arria II GX and GZ transceiver channel architecture.
/2
wrclk
Guide.
/2
Receiver Channel PCS
Transmitter Channel PCS
rdclk
(Note 1)
Arria II Device Handbook Volume 2: Transceivers
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Parallel Recovery Clock
PMA-to-PCS
Interface
Transmitter Channel
Receiver Channel
High-Speed
Serial Clock
PMA
PMA
1–11