EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 93

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
Figure 4–14. Loopback Mode for Half-DSP Block
Note to
(1) Block output for accumulator overflow and saturate overflow.
December 2010 Altera Corporation
Figure
dataa_0[17..0]
datab_0[17..0]
dataa_1[17..0]
datab_1[17..0]
4–14:
1
1
zero_loopback
At compile time, you must select the option to use the loopback mode or the general
two-multiplier adder mode.
If all the inputs are full 18 bits and unsigned, the result requires 37 bits for
two-muliplier adder mode. Because the output data width in two-multiplier adder
mode is limited to 36 bits, this 37-bit output requirement is not allowed. Any other
combination that does not violate the 36-bit maximum result is permitted; for
example, two 16 × 16 signed two-multiplier adders is valid.
Two-multiplier adder mode supports the rounding and saturation logic unit. You can
use pipeline registers and output registers in the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
Half-DSP Block
loopback
clock[3..0]
ena[3..0]
aclr[3..0]
output_saturate
output_round
+
Arria II Device Handbook Volume 1: Device Interfaces and Integration
signa
signb
overflow (1)
result[ ]
4–21