EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 84

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–12
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Pipeline Register Stage
Second-Stage Adder
Rounding and Saturation Stage
1
1
Figure 4–5 on page 4–8
feed or bypass the pipeline registers. Pipeline registers increase the maximum
performance (at the expense of extra cycles of latency) of the DSP block, especially
when using the subsequent DSP block stages. Pipeline registers split up the long
signal path between the input-registers/multiplier/first-stage adder and the
second-stage adder/round-and-saturation/output-registers, creating two shorter
paths.
There are four individual 44-bit second-stage adders per DSP block (two adders per
half-DSP block). You can configure the second-stage adders as either:
■
■
■
■
You can use the chained-output adder at the same time as a second-level adder in
chained output summation mode.
The output of the second-stage adder has the option to go into the rounding and
saturation logic unit or the output register.
You cannot use the second-stage adder independently from the multiplier and
first-stage adder.
Rounding and saturation logic units are located at the output of the 44-bit
second-stage adder (the rounding logic unit followed by the saturation logic unit).
There are two rounding and saturation logic units per half-DSP block. The input to
the rounding and saturation logic unit can come from one of the following stages:
■
■
■
■
These stages are described in
The dynamic rounding and saturation signals control the rounding and saturation
logic unit, respectively. A logic 1 value on the round signal, saturate signal, or both
enables the round logic unit, saturate logic unit, or both.
The final stage of a 36-bit multiplier
A sum of four (18 × 18)
An accumulator (44-bits maximum)
A chained output summation (44-bits maximum)
Output of the multiplier (independent multiply mode in 18 × 18)
Output of the first-stage adder (two-multiplier adder)
Output of the pipeline registers
Output of the second-stage adder (four-multiplier adder, multiply-accumulate
mode in 18 × 18)
shows that the output from the first-stage adder can either
“Arria II Operational Mode Descriptions” on page
Chapter 4: DSP Blocks in Arria II Devices
December 2010 Altera Corporation
DSP Block Resource Descriptions
4–14.