NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 102

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9 0
M E M m o d u l e c o n f i g u r a t i o n
Note:
Table 36: MMCR bit definition
D31:24
D23
D22:21
Bits
15
31
30
14
R/W
R/W
R/W
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
The software reset command issued by the GEN module Software Service
register has no effect on any MEM Module Configuration registers.
29
13
28
12
RFCNT
RCYC
RFCNT
REFEN
Mnemonic
27
11
26
10
25
9
0
0
0
Reset
24
8
Reserved
REFEN
Refresh count value
Refresh period =
[(2*RFCNT + 2) * 2] / F
Defines the refresh period for the memory controller
when FP/EDO DRAM or SDRAM is being used.
All DRAMs require a periodic refresh cycle. You
determine the specific cycle.
Note:
The memory controller generates CAS before RAS
refresh cycles for all DRAM types.
Enable DRAM refresh
0
1
Must be set to 1 when DRAMs are used.
Refresh cycle count
The refresh timing, based on the sample timing
diagram shown in "fp_refresh_cycles" on page 288,
is selected by the value in this field for all chip
selects programmed for FP/EDO DRAM operation.
This field has no effect on SDRAM.
Description
23
7
Disable DRAM refresh
Enable DRAM refresh
22
6
RCYC
There is a small performance and power
penalty for programming a refresh period
smaller than required.
21
5
AMUX
20
XTALE
4
A[27]
19
3
A[26]
18
2
A[25]
17
1
AMUX
16
0
2