NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 232

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2 2 0
G e n e r a l - p u r p o s e I / O c o n f i g u r a t i o n s
General-purpose I/O configurations
Figure 26 shows a two-byte transfer in SPI slave modes 0 and 1. See "Serial internal/
external timing" on page 297 for associated timing values.
Figure 26: SPI slave mode 0 and 1 two-byte transfer
The GEN module provides the physical layer connections for the NMSI (Non
Multiplexed Serial Interface) and SPI interfaces. NMSI is used for the UART protocol.
Use the appropriate GPIO port pins to correspond with the NMSI signals (see "PORTA
Configuration register" on page 73 and "PORTC Configuration register" on page 77).
When NMSI is used with synchronous operation, the RXCA or B and TXCA or B signals
provide the RX and TX clocks, respectively. When NMSI is used with asynchronous
operation, the OUT1A or B and OUT2A or B signals provide the general-purpose
output pin. See "Serial Channel 1, 2 Bit-Rate registers," beginning on page 241, for
more information about this synchronous/asynchronous setting.
SPI CLK Out (mode 0)
SPI CLK Out (mode 1)
residual bytes to the RX FIFO, the buffer and/or character GAP timers must
be used. When either timer expires, any residual RX data bytes are
immediately written to the RX FIFO. Note that some delay will occur in
writing the final residual bytes; the delay is determined by the
configuration of the buffer and character GAP timers.
SPI Data Out
SPI Data In
SPI Enable
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
msb
msb
SPI Slave Mode 0 and 1, (Two Byte Transfer)
lsb
lsb
msb
msb
lsb
lsb