NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 46

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Detail of ARM exceptions
3 4
W o r k i n g w i t h A R M e x c e p t i o n s
All internal ARM7TDMI internal peripherals are presented to the CPU using the IRQ or
FIRQ interrupt inputs. The ARM can mask various ARM7TDMI peripheral interrupts at
the global level, using the ARM7TDMI interrupt controller. The ARM also can mask
interrupts at the micro-level, using configuration features with the peripheral
modules.
All IRQ interrupts are disabled when the I bit is set in the ARM CPSR. When the I bit is
cleared, those interrupts enabled in the ARM7TDMI interrupt controller can assert the
IRQ input to the ARM processor.
The ARM processor sets the I bit automatically when entering an interrupt service
routine (ISR), which disables recursive interrupts. The ISR’s first task is to read the
Interrupt Status register, which identifies all active sources for the IRQ interrupt.
Firmware sets the priorities for servicing interrupts at bootup, using the bits defined
in the Interrupt Status register.
Reset exception
A reset exception is the highest priority exception. When the ARM7TDMI is held in
reset, the processor abandons the executing instruction and continues to fetch
instructions from incrementing word addresses.
When the ARM7TDMI is removed from reset, the processor performs these steps:
1
2
3
4
Undefined exception
When the ARM7TDMI encounters an instruction it cannot handle, it takes the
undefined instruction trap. The undefined instruction trap can extend either the
Thumb or ARM instruction set by software emulation.
Overwrites
current values of the PC and CPSR into them. The values of the saved PC and
SPSR are not defined.
Forces the CPSR M field to
CPSR, and clears the CPSR T bit (back to ARM mode).
Forces the PC to fetch the next instruction from address
Resumes execution in ARM state.
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
R14_svc
and
SPSR_svc
10011
(Saved Processor Status register) by copying the
(supervisor mode), sets the I and F bits in the
’h00
.