NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 251

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 89: Serial Channel Status Register A bit definition
D09
D08
D07
D06
Bits
R/C
R
R/C
R/C
Access
RBC
RFULL
DCDI
RII
Mnemonic
0
0
0
0
Reset
Receive buffer closed interrupt pending
Indicates a receive buffer closed condition. Once set,
the RBC bit remains set until acknowledged. RBC is
acknowledged by writing a 1 to this same bit position
in this register. The RBC bit is acknowledged
automatically by hardware when the receiver is
configured to operate in DMA mode. The RBC status
condition can be programmed to generate an interrupt
by setting the related IE bit in Serial Channel Control
Register A.
The RBC field indicates that bits D31:26 in this
register are valid. While the RBC field is active, the
RRDY field is not. To activate RRDY (to read the
data FIFO), the RBC bit must be acknowledged. This
interlock between RBC and RRDY allows the
firmware driver to read the D31:26 status bits. When
operating in DMA mode, the status bits are written
automatically to the receive DMA buffer descriptor,
and the interlock between RBC and RRDY is handled
automatically in the hardware.
Receive FIFO full
Indicates that the receive data FIFO currently is full.
Change in DCD interrupt pending
Indicates a state change in the EIA data carrier detect
signal. Once set, the DCDI field remains set until
acknowledged. DCDI is acknowledged by writing a 1
to this same bit position in this register.
The DCDI status condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel Control Register A.
Change in RI interrupt pending
Indicates a state change in the EIA ring indicator
signal. Once set, the RII bit remains set until
acknowledged. RII is acknowledged by writing a 1 to
this same bit position in this register.
The RII status condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel Control Register A.
Description
w w w . d i g i e m b e d d e d . c o m
S e r i a l C o n t r o l l e r M o d u l e
2 3 9