NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 163

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Transmit and receive FIFOs
EFE transmit processing
EFE receive processing
EFE logic provides all control and status registers required by the Ethernet module.
The transmitter and receiver each provide a 16-bit status word after processing each
Ethernet frame. These status words can be given to the CPU on an interrupt basis or
moved automatically to the DMA buffer descriptor for the associated Ethernet frame.
The EFE contains a 512-byte transmit FIFO and a 2048-byte local receive FIFO (storing
filtered packets):
The NS7520 Ethernet transmit DMA channel addresses one list of buffer descriptors
per packet to be transmitted. The Ethernet transmit DMA channel moves Ethernet
packets corresponding to this buffer descriptor list to the local FIFO in the EFE
module.
The MAC block receives good Ethernet packets (those with a valid checksum and
size); bad packets (those with invalid checksum, fragment errors, bad size, etc.) are
discarded automatically.
Transmit FIFO. Allows the critical portion of the transmit buffer to wait in
the FIFO while collisions occur on the Ethernet medium. This scheme
removes the need for the transmitter to fetch the buffer multiple times
from memory.
Receive FIFO. Allows the entire Ethernet frame to be received and wait in
the FIFO while the receive byte count is analyzed. The receive byte count is
analyzed to determine the optimum buffer descriptor for DMA transfer. The
DMA channel assigned to the Ethernet receiver can use one of four
differently sized receive buffers. Only successfully received frames, with
acceptable destination addresses, are committed to external system
memory.
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