NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 173

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 53: Ethernet General Control register bit definition
D16
D15:14
D13
D12
D11
D10
Bits
R/W
R/W
N/A
R/W
R/W
R/W
Access
EFULLD
MODE
Reserved
RXCINV
TXCINV
pNA
Mnemonic
0
0
N/A
0
0
0
Reset
Enable full-duplex operation
Set to 1 to allow the Ethernet TX and RX DMA operations
to operate simultaneously. This bit must be set when the
Ethernet link negotiation results in full-duplex mode.
It is recommended that you limit transmit frames to 512
bytes when full-duplex operation is enabled.
Ethernet interface mode
00
10
11
Identifies the type of Ethernet PHY attached to the
NS7520.
In ENDEC SEEQ mode, the LPBK pin is inverted before
driving the MDC pin.
In ENDEC Level 1 mode, the PDN signal is driven using an
open-drain output driver.
Reads as zero.
Invert the receive clock input
Set to 1 only when the external Ethernet PHY generates a
clock that is inverted in phase relative to what the MAC is
expecting.
This bit is not required for most commercially available
PHY devices.
Invert the transmit clock input
Set to 1 only when the external Ethernet PHY generates a
clock that is inverted in phase relative to what the MAC is
expecting.
This bit is not required for most commercially available
PHY devices.
pSOS pNA buffer descriptors
0
1
Description
w w w . d i g i e m b e d d e d . c o m
Standard receiver format. The data block immediately
follows the 14-byte header block.
pSOS pNA receiver format. The receiver inserts a 2-
byte padding between the
14-byte header and the data block. This configuration
aligns both the header and the data blocks on a 32-bit
longword boundary.
10/100 Mbps MII mode
10 Mbps Level 1 ENDEC mode
10 Mbps SEEQ ENDEC mode
E t h e r n e t M o d u l e
1 6 1